RISC-V Gains Ground in AI Accelerator Design as Licensing Costs Squeeze Smaller Chipmakers

RISC-V, the open standard instruction set architecture originally developed at UC Berkeley, has moved well past its early embedded-microcontroller niche into AI accelerator and chiplet design, as chipmakers priced out of Arm's licensing tiers look for a viable alternative that doesn't carry per-unit royalty costs. The architecture's appeal for AI silicon specifically is its extensibility: designers can add custom instructions tuned for matrix multiplication and tensor operations without needing Arm's or x86's cooperation, a flexibility that has drawn interest from accelerator startups that can't afford the licensing overhead a mainstream Arm core would add to every chip shipped. Chinese chip designers have been the most aggressive adopters, partly as a hedge against continued US export controls on Arm-licensed and x86 designs, with several domestic AI accelerator projects built around RISC-V control cores paired with custom tensor units. That geopolitical driver has made RISC-V adoption in China move faster than pure economics alone would predict, since the architecture's open governance means no single company's export policy can cut off access to the instruction set itself. Nvidia and Qualcomm have both increased their own RISC-V investment for auxiliary and control-plane cores inside larger AI accelerator packages — not replacing their primary compute architectures, but using RISC-V for the smaller management and I/O-handling cores where royalty cost matters more than raw performance, a pattern chip industry analysts describe as the most likely path for RISC-V's near-term growth: coexistence inside larger heterogeneous designs rather than an outright replacement for Arm or x86 in performance-critical roles. The remaining gap holding back broader RISC-V adoption in AI workloads is software tooling maturity — compiler optimization, driver support, and the breadth of pre-tuned AI framework kernels available for RISC-V still trail what Arm and x86 have built up over decades, a gap chip designers say is closing but still adds real engineering cost to any RISC-V-based AI accelerator project relative to sticking with an established architecture.