TSMC began volume production of its N2 (2-nanometre class) process node in Q2 2026, and the early yield data has surprised analysts. Industry sources tracking wafer starts at TSMC's Hsinchu fabs put functional yield above 55 percent at the point of volume entry — compared with the roughly 40 percent yield that N3 achieved at an equivalent production stage in late 2022.
The improvement comes from two structural changes. First, TSMC adopted Gate-All-Around (GAA) transistors for N2, replacing the FinFET architecture used through N3. GAA surrounds the channel on all four sides rather than three, giving the gate better electrostatic control and reducing leakage at smaller geometries. Second, TSMC refined its EUV (extreme ultraviolet) lithography process to reduce multi-patterning steps, which cuts variability and improves consistency across the wafer.
Apple is TSMC's first N2 volume customer, with M5 and A19 Pro chips fabbed on the new node. The performance-per-watt improvement over N3E is quoted at approximately 15 percent for the same transistor density, or around 25 percent density improvement at iso-performance. In practical terms, that means an A19 Pro can deliver roughly the same peak performance as A18 Pro at meaningfully lower battery draw.
For the AI hardware market, N2 availability matters because it expands what is physically possible in a mobile form factor. The neural engine throughput gains in M5 are partly a product of transistor density — more compute logic fits in the same die area. Qualcomm's next-generation Snapdragon for late 2026 flagship Android devices is also confirmed for N2.
The downstream effect on pricing will take 18 to 24 months to materialise. N2 wafer costs are estimated at $20,000 to $25,000 per wafer — roughly 15 percent above N3E — but the die area efficiency means per-chip cost for high-volume parts should be comparable or better by mid-2027 as yields improve further.
Intel and Samsung remain behind. Intel's own 18A node (their first internal GAA process) is in risk production with customer samples but has not entered volume. Samsung's SF2 (2nm) faced repeated delays and is not expected in volume until late 2026 at the earliest. TSMC's sustained manufacturing lead — measured in yield-at-launch — is the defining competitive moat in the semiconductor industry right now.